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80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer product specification supersedes data of 1998 jan 19 ic20 data handbook 1998 may 01 integrated circuits
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 2 1998 may 01 853-1568 19329 description the philips 8xc550 is a high-performance microcontroller fabricated with philips high-density cmos technology. this philips cmos technology combines the high speed and density characteristics of hmos with the low power attributes of cmos. philips epitaxial substrate minimizes latch-up sensitivity. the cmos 8xc550 has the same instruction set as the 80c51. the 8xc550 contains a 4k 8 eprom (87c550)/rom (83c550)/romless (80c550 has no program memory on-chip), a 128 8 ram, 8 channels of 8-bit a/d, four 8-bit ports (port 1 is input only), a watchdog timer, two 16-bit counter/timers, a seven-source, two-priority level nested interrupt structure, a serial i/o port for either multi-processor communications, i/o expansion or full duplex uart, and an on-chip oscillator and clock circuits. in addition, the 8xc550 has two software selectable modes of power reductioneidle mode and power-down mode. the idle mode freezes the cpu while allowing the ram, timers, serial port, and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. features ? 80c51 based architecture 4k 8 eprom (87c550)/rom (83c550) 128 8 ram eight channels of 8-bit a/d two 16-bit counter/timers watchdog timer full duplex serial channel boolean processor ? memory addressing capability 64k rom and 64k ram ? power control modes: idle mode power-down mode ? cmos and ttl compatible ? one speed range at v cc = 5v 10% 3.5 to 16mhz ? extended temperature ranges ? otp package available ordering information romless rom eprom temperature range c and package 1 freq mhz drawing number p80c550ebp n p83c550ebp n p87c550ebp n otp 0 to +70, plastic dual in-line package 3.5 to 16 sot129-1 p80c550eba a p83c550eba a p87c550eba a otp 0 to +70, plastic leaded chip carrier 3.5 to 16 sot187-2 p80c550efa a p83c550efa a p87c550efa a otp 40 to +85, plastic leaded chip carrier 3.5 to 16 sot187-2 notes: 1. otp = one time programmable eprom.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 3 block diagram psen ea /v pp ale/prog rst xtal1 xtal2 v cc v ss port 0 drivers port 2 drivers ram addr register ram port 0 latch port 2 latch rom/eprom register b acc stack pointer tmp2 tmp1 alu timing and control instruction register pd oscillator psw port 1 latch port 3 latch port 1 drivers port 3 drivers program address register buffer pc incre- menter program counter dptr pcon scon tmod tcon th0 tl0 th1 tl1 sbuf ie ip interrupt, serial port and timer blocks p1.0p1.7 p3.0p3.7 p0.0p0.7 p2.0p2.7 su00005
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 4 pin configurations plastic leaded chip carrier 6140 7 17 39 29 18 28 pin function 1av cc 2 vref+ 3 vref 4av ss 5 p1.0/adc0 6 p1.1/adc1 7 p1.2/adc2 8 p1.3/adc3 9 p1.4/adc4 10 p1.5/adc5 11 p1.6/adc6 12 p1.7/adc7 13 rst 14 p3.0/rxd 15 p3.1/txd pin function 16 p3.2/int0 17 p3.3/int1 18 p3.4/t0 19 p3.5/t1 20 p3.6/wr 21 p3.7/rd 22 xtal2 23 xtal1 24 v ss 25 p2.0/a8 26 p2.1/a9 27 p2.2/a10 28 p2.3/a11 29 p2.4/a12 30 p2.5/a13 pin function 31 p2.6/a14 32 p2.7/a15 33 psen 34 ale/prog 35 ea /v pp 36 p0.7/ad7 37 p0.6/ad6 38 p0.5/ad5 39 p0.4/ad4 40 p0.3/ad3 41 p0.2/ad2 42 p0.1/ad1 43 p0.0/ad0 44 v cc su00196 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 av cc /vref+ av ss /vref p1.0/adc0 p1.1/adc1 p1.2/adc2 p1.3/adc3 p1.4/adc4 rst rxd/p3.0 txd/p3.1 int0 /p3.2 int1 /p3.3 t0/p3.4 t1/p3.5 p1.5/adc5 wr /p3.6 rd /p3.7 xtal2 xtal1 v ss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p2.5/a13 p2.6/a14 p2.7/a15 psen ale/prog ea /v pp p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 v cc plastic dual in-line package
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 5 pin description pin no. mnemonic dip lcc type name and function v ss 20 24 i ground: 0v reference. v cc 40 44 i power supply: this is the power supply voltage for normal, idle, and power-down operation. av cc 1 1 i analog power supply: analog supply voltage. av ss 2 4 i analog ground: analog 0v reference. vref+ vref 2 3 i i vref: a/d converter reference level inputs. note that these references are combined with av cc and av ss in the 40-pin dip package. p0.00.7 3932 4336 i/o port 0: port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. port 0 also outputs the code bytes during program verification in the s87c550. external pull-ups are required during program verification. p1.0p1.7 38 512 i port 1: port 1 is an 8-bit input only port (6-bit in the dip package; bits p1.6 and p1.7 are not implemented). port 1 digital input can be read out any time. adc0adc7 38 512 adcx: inputs to the analog multiplexer input of the 8-bit a/d. there are only six a/d inputs in the dip package. p2.0p2.7 2128 2532 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (mov @ri), port 2 emits the contents of the p2 special function register. p3.0p3.7 1017 1421 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also serves the special features of the sc80c51 family, as listed below: 10 14 i rxd (p3.0): serial input port 11 15 o txd (p3.1): serial output port 12 16 i int0 (p3.2): external interrupt 13 17 i int1 (p3.3): external interrupt 14 18 i t0 (p3.4): timer 0 external input 15 19 i t1 (p3.5): timer 1 external input 16 20 o wr (p3.6): external data memory write strobe 17 21 o rd (p3.7): external data memory read strobe rst 9 13 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc . ale/prog 30 34 i/o address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input (prog ) during eprom programming. psen 29 33 o program store enable: the read strobe to external program memory. when the device is executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea /v pp 31 35 i external access enable/programming supply voltage: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to 0fffh. if ea is held high, the device executes from internal program memory unless the program counter contains an address greater than 0fffh. for the 80c550 romless part, ea must be held low for the part to operate properly. this pin also receives the 12.75v programming supply voltage (v pp ) during eprom programming. xtal1 19 23 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 18 22 o crystal 2: output from the inverting oscillator amplifier.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 6 table 1. 8xc550 special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h adat# a/d result c6h xxh adcon# a/d control c5h adci adcs aadr2 aadr1 aadr0 xxx00000b b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h dptr: dph dpl data pointer (2 bytes): high byte low byte 83h 82h 00h 00h bf be bd bc bb ba b9 b8 ip*# interrupt priority b8h pwd pad ps pt1 px1 pt0 px0 x0000000b af ae ad ac ab aa a9 a8 ie*# interrupt enable a8h ea ewd ead es et1 ex1 et0 ex0 00h p0* port 0 80h 87 86 85 84 83 82 81 80 ffh p1* port 1 90h 97 96 95 94 93 92 91 90 ffh p2* port 2 a0h a7 a6 a5 a4 a3 a2 a1 a0 ffh p3* port 3 b0h b7 b6 b5 b4 b3 b2 b1 b 0 ffh pcon# power control 87h smod sidl gf1 gf0 pd idl 00xx0000b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov p 00h sbuf serial data buffer 99h xxh 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 00h tcon* timer counter/control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tmod timer/counter mode 89h gate c/t m1 m0 gate c/t m1 m0 00h th0 timer 0 high byte 8ch 00h th1 timer 1 high byte 8dh 00h tl0 timer 0 low byte 8ah 00h tl1 timer 1 low byte 8bh 00h c7 c6 c5 c4 c3 c2 c1 c0 wdcon*# watchdog timer control c0h pre2 pre1 pre0 wdrun wdtof wdmod 000xx000b** wdl# watchdog timer reload c1h ffh** wfeed1# watchdog timer feed 1 c2h xxh wfeed2# watchdog timer feed 2 c3h xxh * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. **this value is not valid for a masked rom part (83c550) when running from internal memory (ea = 1). see data sheet for details.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 7 smod sidl x x gf1 gf0 pd idl lsb msb note: the pcon register is at sfr byte address 87h. its contents following a reset are 00xx0000. bit symbol function pcon.7 smod double baud rate pcon.6 sidl serial port idle pcon.5 x reserved for future use pcon.4 x reserved for future use pcon.3 gf1 general purpose flag bit pcon.2 gf0 general purpose flag bit pcon.1 pd power down bit pcon.0 idl idle mode bit su00197 figure 1. power control register (pcon) xxx adci adcs aadr2 aadr1 aadr0 lsb msb bit symbol function adcon.7 e not used adcon.6 e not used adcon.5 e not used adcon.4 adci adc interrupt flag. this flag is set when an adc conversion result is ready to be read. an interrupt is invoked if the a/d interrupt is enabled. the flag must be cleared by software. it cannot be set by software. adcon.3 adcs adc start and status. setting this flag starts an a/d conversion. the adc logic insures that this signal is high while the adc is busy. on completion of the conversion, adcs is reset at the same time the interrupt flag adci is set. adcs cannot be reset by software. adcon.2 addr2 analog input select 2 adcon.1 addr1 analog input select 1 adcon.0 addr0 analog input select 0 su00198 input channel selection addr2 addr1 addr0 input pin 0 0 0 adc0 0 0 1 adc1 0 1 0 adc2 0 1 1 adc3 1 0 0 adc4 1 0 1 adc5 1 1 0 adc6 1 1 1 adc7 figure 2. a/d control register (adcon)
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 8 a/d converter the analog input circuitry consists of an 8-input analog multiplexer and an analog-to-digital converter with 8-bit resolution. in the lcc package, the analog reference voltage and analog power supplies are connected via separate input pins; in the dip package, vref+ is combined with av cc and vref is combined with av ss . the analog inputs are alternate functions to port 1, which is an input only port. digital input to port 1 can be read any time during an a/d conversion. care should be exercised in mixing analog and digital signals on port 1, because cross talk from the digital input signals can degrade the a/d conversion accuracy of the analog input. an a/d conversion requires 40 machine cycles. the a/d converter is controlled by the adcon special function register. the input channel to be converted is selected by the analog multiplexer by setting adcon register bits, addr2addr0 (see figure 2). these bits can only be changed when adci and adcs are both low. the completion of the 8-bit adc conversion is flagged by adci in the adcon register and the result is stored in the special function register adat. an adc conversion in progress is unaffected by a software adc start. the result of a completed conversion remains unaffected provided adci remains at a logic 1. while adcs is a logic 1 or adci is a logic 1, a new adc start will be blocked and consequently lost. an a/d conversion in progress will be aborted when the idle or power-down mode is entered. the result of a completed conversion (adci = logic 1) remains unaffected when entering the idle mode, but will be lost if power-down mode is entered. see figure 3 for the a/d input equivalent circuit. the analog input pins adc0-adc7 may still be used as digital inputs. the analog input channel that is selected by the addr2-addr0 bits in adcon cannot be used as a digital input. reading the selected a/d channel as a digital input will always return a 1. the unselected a/d inputs may always be used as digital inputs. on reset the a/d port pins are set to the digital mode and will work as a normal port and need no further initialization. to use the a/d converter a single byte should be written to adcon which selects the a/d mux and concurrently sets the adcs bit to start the a/d conversion. the 40 machine cycles of the a/d conversion include time for signal settling after the mux is selected and before the sample and hold procedure is completed. the circuitry which disables the digital buffer from the port pin is updated at the start of an a/d conversion by setting the adcs bit in adcon. after powerup, problems will occur the first time that adcon is written to if adcs is not set; in this case, the digital signal disable registers contain random data and some o the 8 port pins will have their digital buffers disabled. when read, these disabled buffers will ignore their input and only return a 1. this condition will be corrected by writing a 1 to adcs in adcon which starts and a/d conversion. thus, there are two operating modes: 1. digital only - no analog inputs are used and adcon is never written to. in this case pins adc0-adc7 are configured as digital inputs. 2. a/d converter used - the input multiplexer select field must be written to and adcs must be set in adcon. this allows unselected a/d inputs to be used as digital inputs. adcon register msb lsb x x x adci sdcs aadr2 aadr1 aadr0 adci adcs operation 0 0 adc not busy, a conversion can be started. 0 1 adc busy, start of a new conversion is blocked. 1 0 conversion completed, start of a new is blocked. 1 1 not possible. input channel selection addr2 addr1 addr0 input pin 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6* p1.7* *not present on 40-pin dip versions. symbol position function adci adcon.4 adc interrupt flag. this flag is set when an adc conversion is complete. if ie.5 = 1, an interrupt is requested when adci = 1. the adci flag must be cleared by software after a/d data is read, before the next conversion can begin. adcs adcon.3 adc start and status. setting this bit starts an a/d conversion. once set, adcs remains high throughout the conversion cycle. on completion of the conversion, it is reset at the same time the adci interrupt flag is set. adcs cannot be reset by software. aadr2 adcon.2 analog input selects. aadr1 adcon.1 binary coded address aadr0 adcon.0 selects one of the five analog input port pins of p1 to be input to the converter. it can only be changed when adci and adcs are both low. aadr2 is the most significant bit.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 9 sample a/d routines the following routines demonstrate two methods of operating the a/d converter. the first method uses polling to determine when the a/d conversion is complete. the second method uses the a/d interrupt to flag the end of conversion. the routine readad will start a read of the a/d channel identified by r7, and wait for the conversion to complete, polling the a/d interrupt flag. the result is returned in the accumulator. readad:mov a,#08h ;basic a/d start command. orl a,r7 ;add channel # to be read. mov adcon,a; ;start a/d. adloop: mov a,adcon ;get a/d status. jnb acc.4,adloop;wait for adci (a/d ;finished). mov a,adat ;get conversion result mov adcon,#0 ;clear adci. ret the routine startad will start a read of the a/d channel identified by r7 and exit back to the calling program. when the conversion is complete, the a/d interrupt occurs, calling the a/d interrupt service routine. the result of the conversion is returned in register r6. startad: mov a,#08h ;basic a/d start command. orl a,r7 ;add channel # to be read. mov adcon,a ;start a/d. ret . . . org 2bh ;a/d interrupt address. adint: mov r6,adat ;get conversion result. mov adcon,#0 ;clear adci. reti r s v analog input c s c c to comparator + i n i n+1 sm n+1 sm n rm n+1 rm n multiplexer rm = 0.5 - 3 k w cs + cc = 15pf maximum rs = recommended < 9.6 k w for 1 lsb @ 12mhz note: because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. when a conversio n is initiated, switch sm closes for 8tcy (8 m s @ 12mhz crystal frequency) during which time capacitance cs + cc is charged. it should be noted that the sampling causes the analog input to present a varying load to an analog source. su00199 figure 3. a/d input: equivalent circuit
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 10 a/d converter parameter definitions the following definitions are included to clarify some specifications given and do not represent a complete set of a/d parameter definitions. absolute accuracy error absolute accuracy error of a given output is the difference between the theoretical analog input voltage to produce a given output and the actual analog input voltage required to produce the same code. since the same output code is produced by a band of input voltages, the arequired input voltageo is defined as the midpoint of the band of input voltage that will produce that code. absolute accuracy error not specified with a code is the maximum over all codes. nonlinearity if a straight line is drawn between the end points of the actual converter characteristics such that zero offset and full scale errors are removed, then non-linearity is the maximum deviation of the code transitions of the actual characteristics from that of the straight line so constructed. this is also referred to as relative accuracy and also integral non-linearity. differential non-linearity differential non-linearity is the maximum difference between the actual and ideal code widths fo the converter. the code widths are the differences expressed in lsb between the code transition points, as the input voltage is varied through the range for the complete set of codes. gain error gain error is the deviation between the ideal and actual analog input voltage required to cause the final code transition to a full-scale output code after the offset error has been removed. this may sometimes be referred to as full scale error. offset error offset error is the difference between the actual input voltage that causes the first code transition and the ideal value to cause the first code transition. this ideal value is 1/2 lsb above v ref . channel to channel matching channel to channel matching is the maximum difference between the corresponding code transitions of the actual characteristics taken from different channels under the same temperature, voltage and frequency conditions. crosstalk crosstalk is the measured level of a signal at the output of the converter resulting from a signal applied to one deselected channel. total error maximum deviation of any step point from a line connecting the ideal first transition point to the ideal last transition point. relative accuracy relative accuracy error is the deviation of the adc's actual code transition points from the ideal code transition points on a straight line which connects the ideal first code transition point and the final code transition point, after nullifying offset error and gain error. it is generally expressed in lsbs or in percent of fsr. watchdog timer the purpose of the watchdog timer is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state, possibly due to a programming error, electrical noise, or rfi. when enabled, the watchdog circuit will generate a system reset if the user program fails to afeedo (or reload) the watchdog within a predetermined amount of time. the watchdog timer implemented on the 8xc550 has a programmable interval and can thus be fine tuned to a particular application. if the watchdog function is not used, the timer may still be used as a versatile general purpose timer. the watchdog function consists of a programmable 13-bit prescaler, and an 8-bit main timer. the main timer is clocked by a tap taken from one of the top 8 bits of the prescaler. the prescaler is incremented once every machine cycle, or 1/12 of the oscillator frequency. thus, the main counter can be clocked as often as once every 64 machine cycles or as seldom as once every 8192 machine cycles. when clocked, the main counter decrements. if the main watchdog counter reaches zero, a system reset will occur. to prevent the watchdog timer from under-flowing, the watchdog must be fed before it counts down to zero. when the watchdog is fed, the contents of the wdl register are loaded into the main watchdog counter and the prescaler is cleared. wdcon register msb lsb pre2 pre1 pre0 x x wdrun wdtof wdmod symbol position function wdcon.7 pre2 prescaler select (read/write). wdcon.6 pre1 these bits select theprescaler divide ratio wdcon.5 pre0 according to the following table: pre2 pre1 pre0 divisor (from f osc ) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 12 64 12 64 2 12 64 4 12 64 8 12 64 16 12 64 32 12 64 64 12 64 128 wdcon.4 not used wdcon.3 not used wdcon.2 wdrun run control (read/write). this bit turns the timer on (wdrun = 1) or off (wdrun = 0) if the timer mode has been selected. wdcon.1 wdtof timeout flag (read/write). this bit is set when the watchdog timer underflows. it is cleared by an external reset and can be cleared by software. wdcon.0 wdmod mode selection (read/write). when wdmod = 1, the watchdog is selected; when wdmod = 0, the timer is selected. selecting the watchdog mode automatically disables power-down mode. wdmod is cleared by external reset. once the watchdog mode is selected, this bit can only be cleared by writing a 0 to this bit and then performing a feed operation.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 11 a very specific sequence of events must take place to feed the watchdog timer; it cannot be fed accidentally by a runaway program. the following routines demonstrate setting up and feeding the watchdog timer. these routines apply to all versions of the 8xc550 except the rom part when running from internal program memory. this routine sets up and starts the watchdog timer. this is not necessary for internal rom operation, because setup of the watchdog timer on masked rom parts is accomplished directly via rom mask options. setwd: mov wdl,#0ffh ;set watchdog reload value. mov wdcon,#0e5;set up timer prescaler, mode, and ;run bits. acall feedwd ;start watchdog with a feed ;operation. ret this routine executes a watchdog timer feed operation, causing the timer to reload from wdl. interrupts must be disabled during this operation due to the fact that the two feed registers must be loaded on consecutive instruction cycles, or a system reset will occur immediately. feedwd: clr ea ;this sequence must not be ;interrupted. mov wfeed1,#0a5h;first instruction of feed sequence. mov wfeed2,#05ah;second instruction of feed ;sequence. setb ea ;turn interrupts back on. ret an interrupt is available to allow the watchdog timer to be used as a general purpose timer in applications where the watchdog function is not needed. the timer operates in the same manner when used as a general purpose timer except that the timer interrupt is generated on timer underflow instead of a chip reset. refer to the 87c550 data sheet for additional information on watchdog timer operation. programming the watchdog timer both the eprom and rom devices have a set of sfrs for holding the watchdog autoload values and the control bits. the watchdog time-out flag is present in the watchdog control register and operates the same in all versions. in the eprom device, the watchdog parameters (autoload value and control) are always taken from the sfrs. in the rom device, the watchdog parameters can be mask programmed or taken from the sfrs. the selection to take the watchdog parameters from the sfrs or from the mask programmed values is controlled by ea (external access). when ea is high (internal rom access), the watchdog parameters are taken from the mask programmed values. if the watchdog is masked programmed to the timer mode, then the autoload values and the pre-scaler taps are taken from the sfrs. when ea is low (external access), the watchdog parameters are taken from the sfrs. the user should be able to leave code in his program which initializes the watchdog sfrs even though he has migrated to the mask rom part. this allows no code changes from eprom prototyping to rom coded production parts. watchdog detailed operation eprom device (and romless operation: ea = 0) in the romless operation (rom part, ea = 0) and in the eprom device, the watchdog operates in the following manner. whether the watchdog is in the watchdog or timer mode, when external reset is applied, the following takes place: watchdog mode bit set to timer mode. watchdog run control bit set to off. autoload register set to ff (max count). watchdog time-out flag cleared. prescaler is cleared. prescaler tap set to the highest divide. autoload takes place. the watchdog can be fed even though it is in the timer mode. note that the operational concept is for the watchdog mode of operation, when coming out of a hardware reset, the software should load the autoload registers, set the mode to watchdog, and then feed the watchdog (cause an autoload). the watchdog will now be starting at a known point. if the watchdog is in the watchdog mode and running and happens to underflow at the time the external reset is applied, the watchdog time-out flag will be cleared. when the watchdog is in the watchdog mode and the watchdog underflows, the following action takes place: autoload takes place. watchdog time-out flag is set timer mode interrupt flag unchanged. mode bit unchanged. watchdog run bit unchanged. autoload register unchanged. prescaler tap unchanged. all other device action same as external reset. note that if the watchdog underflows, the program counter will start from 00h as in the case of an external reset. the watchdog time-out flag can be examined to determine if the watchdog has caused the reset condition. the watchdog time-out flag bit can be cleared by software. when the watchdog is in the timer mode and the timer software underflows, the following action takes place: autoload takes place. watchdog time-out flag is set mode bit unchanged. watchdog run bit unchanged. autoload register unchanged. prescaler tap unchanged. the timer mode interrupt flag is cleared when the interrupt routine is invoked. this bit can also be cleared directly by software without a software feed operation. mask rom device (ea = 1) in the mask rom device, the watchdog mode bit (wdmod) is mask programmed and the bit in the watchdog command register is read only and reflects the mask programmed selection. if the mask programmed mode bit selects the timer mode, then the watchdog run bit (wdrun) operates as described under eprom device. if the mask programmed bit selects the watchdog mode, then the watchdog run bit has no effect on the timer operation.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 12 watchdog function the watchdog consists of a programmable prescaler and the main timer. the prescaler derives its clock from the on-chip oscillator. the prescaler consists of a divide by 12 followed by a 13 stage counter with taps from stage 6 through stage 13. the tap selection is programmable. the watchdog main counter is a down counter clocked (decremented) each time the programmable prescaler underflows. the watchdog generates an underflow signal (and is autoloaded) when the watchdog is at count 0 and the clock to decrement the watchdog occurs. the watchdog is 8 bits long and the autoload value can range from 0 to ffh. (the autoload value of 0 is permissible since the prescaler is cleared upon autoload). this leads to the following user design equations. definitions: t osc is the oscillator period, n is the selected prescaler tap value, w is the main counter autoload value, t min is the minimum watchdog time-out value (when the autoload value is 0), t max is the maximum time-out value (when the autoload value is ffh), t d is the design time-out value. t min = t osc 12 64 t max = t min 128 256 t d = t min 2 prescaler w (where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7) note that the design procedure is anticipated to be as follows. a t max will be chosen either from equipment or operation considerations and will most likely be the next convenient value higher than t d . (if the watchdog were inadvertently to start from ffh, an overflow would be guaranteed, barring other anomalies, to occur within t max ). then the value for the prescaler would be chosen from: prescaler = log2 (t max / (t osc 12 256)) 6 this then also fixes t min . an autoload value would then be chosen from: w = t d / t min 1 the software must be written so that a feed operation takes place every t d seconds from the last feed operation. some tradeoffs may need to be made. it is not advisable to include feed operations in minor loops or in subroutines unless the feed operation is a specific subroutine. interrupts the 8xc550 interrupt structure is a seven-source, two-priority level interrupt system similar to that of the standard 80c51 microcontroller. the interrupt sources are listed below in the order of their internal polling sequence. this is the order in which simultaneous interrupts of the same priority level would be serviced. interrupt priorities priority source vector address function highest int0 0003h external interrupt 0 tf0 000bh counter/timer 0 overflow int1 0013h external interrupt 1 tf1 001bh counter/timer 1 overflow ti & ri 0023h serial port transmit/receive adci 002bh a/d converter conversion complete lowest wdtof 0033h watchdog timer overflow (only when not in watchdog mode) interrupt control registers the standard 80c51 interrupt enable and priority registers have been modified slightly to take into account the additional interrupt sources of the 8xc550. interrupt enable register msb lsb ea ewd ead es et1 ex1 et0 ex0 symbol position function ea ie.7 global interrupt enable ewd ie.6 watchdog timer overflow ead ie.5 a/d conversion complete es ie.4 serial port transmit or receive et1 ie.3 timer 1 overflow ex1 ie.2 external interrupt 1 et0 ie.1 timer 0 overflow ex0 ie.0 external interrupt 0 interrupt priority register msb lsb pwd pad ps pt1 px1 pt0 px0 symbol position function pwd ip.6 watchdog timer pad ip.5 a/d conversion ps ip.4 serial port interrupt pt1 ip.3 timer 1 interrupt px1 ip.2 external interrupt 1 pt0 ip.1 timer 0 interrupt px0 ip.0 external interrupt 0 power-down and idle modes the 8xc550 includes the standard 80c51 power-down and idle modes of reduced power consumption. in addition, the 8xc550 includes an option to separately turn off the serial port for extra power savings when it is not needed. also, the individual functional blocks such as the counter/timers are automatically disabled when they are not running. this actually turns off the clocks to the block in question, resulting in additional power savings. note that when the watchdog timer is operating, the processor is inhibited from entering the power-down mode. this is due to the fact that the oscillator is stopped in the power-down mode, which would effectively turn off the watchdog timer. in keeping with the purpose of the watchdog timer, the processor is prevented from accidentally entering power-down due to some erroneous operation. power control register msb lsb smod sidl gf1 gf0 pd idl symbol position function smod pcon.7 double baud rate bit. when set to a 1 and timer 1 is used to generate baud rate, and the serial port is used in modes 1, 2, or 3. sidl pcon.6 separately idles the serial port for additional power savings. pcon.5 reserved pcon.4 reserved gf1 pcon.3 general-purpose flag bit. gf0 pcon.2 general-purpose flag bit. pd pcon.1 power-down bit. starting this bit activates power-down operation. idl pcon.0 idle mode bit. setting this bit activates idle mode operation. if 1s are written to pd and idl at the same time, pd takes precedence.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 13 oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator, as shown in the block diagram, page 3). to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however, minimum and maximum high and low times specified in the data sheet must be observed. idle mode in idle mode, the cpu puts itself to sleep while all of the on-chip peripherals except the a/d stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. an a/d conversion in progress will be aborted when idle mode is entered. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. programmable idle modes the programmable idle modes have been dispersed throughout the functional blocks. each block has its own ability to be disabled. for example, if timer 0 is not commanded to be running (tr = 0), then the clock to the timer is disabled resulting in an idle mode power saving. an additional idle control bit has been added to the serial communications port. a/d operation in idle mode when in the idle mode, the a/d converter will be disabled. however, the current through the v ref pins will be present and will not be reduced internally in either the idle or the power-down modes. it is the responsibility of the user to disconnect v ref to reduce power supply current. pre2 pre1 pre0 x x wdrun wdtof wdmod lsb msb bit symbol function wdcon.7 pre2 prescaler select (read/write). wdcon.6 pre1 prescaler select (read/write). wdcon.5 pre0 prescaler select (read/write). thses bits select the prescaler divide ratio according to the following table: divisor pre2 pre1 pre0 (from f osc ) 0 0 0 12 x 64 0 0 1 12 x 64 x 2 0 1 0 12 x 64 x 4 0 1 1 12 x 64 x 8 1 0 0 12 x 64 x 16 1 0 1 12 x 64 x 32 1 1 0 12 x 64 x 64 1 1 1 12 x 64 x 128 wdcon.4 e not used. wdcon.3 e not used. wdcon.2 wdrun run control (read/write). this bit turns the timer on (wdrun = 1) or off (wdrun = 0) if the timer mode has been selected. wdcon.1 wdtof timeout flag (read/write). this bit is set when the watchdog timer underflows. it is cleared by an external reset and can be cleared by software. wdcon.0 wdmod mode selection (read/write). when wdmod = 1, the watchdog mode is selected; when wdmod = 0, the timer mode is selected. selecting the watchdog mode automatically disables power-down mode. wdmod is cleared by external reset. once the watchdog mode is selected, this bit can only be cleared by writing a 0 to this bit and then performing a feed operation. su00200 figure 4. watchdog control register (wdcon)
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 14 design considerations at power-on, the voltage on v cc and rst must come up at the same time for a proper start-up. when the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. table 2 shows the state of i/o ports during low current operating modes. encryption table the encryption table is a feature of the 83c550 and 87c550 that protects the code from being easily read by anyone other than the programmer. the encryption table is 32 bytes of code that are exclusive nored with the program code data as it is read out. the first byte is xnored with the first location read, the second with the second read, etc. after the encryption table has been programmed, the user has to know its contents in order to correctly decode the program code data. the encryption table itself cannot be read out. for the eprom (87c550) part, the encryption table is programmed in the same manner as the program memory, but using the apgm encryption tableo levels specified in table 4. after the encryption table is programmed, verification cycles will produce only encrypted information. for the rom part (83c550) the encryption table information is submitted with the rom code as shown in table 3. security bits there are two security bits on the 83c550 and 87c550 that, when set, prevent the program data memory from being read out or programmed further. after the first security bit is programmed, the external movc instruction is disabled, and for the 87c550, further programming of the code memory or the encryption table is disabled. the other security bit can of course still be programmed. with only security bit one programmed, the memory can still be read out for program verification. after the second security bit is programmed, it is no longer possible to read out (verify) the program memory. to program the security bits for the 87c550, repeat the programming sequence using the apgm security bito levels specified in table 4. for the masked rom 83c550 the security bit information is submitted with the rom code as shown in table 3. rom code submission when submitting a rom code for the 83c550, the following must be specified: 1. the 4k byte user rom program. 2. the 32 byte rom encryption key. 3. the rom security bits. 4. the watchdog timer parameters. this information can be submitted in an eprom (2764) or hex file with the format specified in table 3. table 2. external pin status during idle and power-down modes mode program memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data table 3. rom code submittal requirements address content bit(s) comment 0000h to 0fffh data 7:0 user rom data 1000h to 101fh key 7:0 rom encryption key; ffh = no encryption 1020h security bit 0 rom security bit 1 1020h security bit 1 rom security bit 2 0 = enable security feature 1 = disable security feature 1030h wdcon 1 7:5 pre2:0 1030h wdcon 1 4 not used 1030h wdcon 1 3 not used 1030h wdcon 1 2 wdrun = 0, not rom coded 1030h wdcon 1 1 wdtof = 0, not rom coded 1030h wdcon 1 0 wdmod 1031h not used 1032h wd 7:0 watchdog autoload value (see specification) note: 1. see watchdog timer specification for definition of wdl and wdcon bits.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 15 electrical deviations from commercial specifications for extended temperature range dc and ac parameters not included here are the same as in the commercial temperature range table. dc electrical characteristics t amb = 40 c to +85 c, v cc = 5v 10% (87c550), v cc = 5v 20% (80/83c550), v ss = 0v test limits symbol parameter conditions min max unit v il input low voltage, except ea 0.5 0.2v cc 0.15 v v il1 input low voltage to ea 0 0.2v cc 0.35 v v ih input high voltage, except xtal1, rst 0.2v cc +1 v cc +0.5 v v ih1 input high voltage to xtal1, rst 0.7v cc +0.1 v cc +0.5 v i il logical 0 input current, ports 2, 3 v in = 0.45v 75 m a i tl logical 1-to-0 transition current, ports 2, 3 v in = 2.0v 750 m a i cc power supply current: active mode idle mode power down mode v cc = 4.55.5v, frequency range = 3.5 to 16mhz 35 6 50 ma ma m a adc dc electrical characteristics av cc = 5v 10%, av ss = 0v, t amb = 40 c to 85 c, unless otherwise specified test limits symbol parameter conditions min max unit av cc analog supply av cc = v cc 0.2 4.5 5.5 v v ref analog reference; av ref + av ref av ss 0.2 av cc + 0.2 v ai cc analog operating supply current see note 1 3.0 ma av in analog input voltage av ss 0.2 av cc + 0.2 v a ic , c ia analog input capacitance 15 pf t ads sampling time 8t cy t adc conversion time 40t cy ae absolute voltage error 1.5 lsb e ra relative accuracy 1 lsb ose offset error see note 1 1 lsb ge gain error see note 1 0.4 % m ctc channel-to-channel matching 1 lsb ct crosstalk 0 100khz 60 db rref resistance between av ref+ and av ref 1.0 10.0 k w ai id idle mode supply current see note 4 50 m a ai pd power down supply current see note 4 50 m a notes: 1. conditions: v ref+ = 4.99712v, v ref = 0v. ai cc value does not include the resistor ladder current. for the 40-pin package, where the v ref inputs are connected to av cc and av ss , the current ai cc will be increased by the register ladder current and may exceed the maximum shown here. 2. the resistor ladder network is not disconnected in the power-down or idle modes. thus to conserve power, the user must remove av cc and v ref+ . 3. if the a/d function is not required, or if the a/d function is only needed periodically, av cc can be removed without affecting the operation of the digital circuitry. contents of adcon and adat are not guaranteed to be valid. digital inputs p1.0 to p1.7 will not function normally. no digital outputs are present on these pins. 4. for this test, the analog inputs must be at the supplies (either v dd or v ss ).
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 16 absolute maximum ratings 1, 2, 3 parameter rating unit operating temperature under bias 40 to +85 c storage temperature range 65 to +150 c voltage on ea /v pp pin to v ss (87c550 only) 0 to +13.0 v voltage on any other pin to v ss 0.5 to +6.5 v input, output current on any two i/o pins 10 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. dc electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 10% (87c550), v cc = 5v 20% (80/83c550), v ss = 0v test limits symbol parameter conditions min typical 1 max unit v il input low voltage, except ea 7 0.5 0.2v cc 0.1 v v il1 input low voltage to ea 7 0 0.2v cc 0.3 v v ih input high voltage, except xtal1, rst 7 0.2v cc +0.9 v cc +0.5 v v ih1 input high voltage, xtal1, rst 7 0.7v cc v cc +0.5 v v ol output low voltage, ports 2, 3 i ol = 1.6ma 2 0.45 v v ol1 output low voltage, port 0, ale, psen i ol = 3.2ma 2 0.45 v v oh output high voltage, ports 2, 3, ale, psen 3 i oh = 60 m a, i oh = 25 m a i oh = 10 m a 2.4 0.75v cc 0.9v cc v v v v oh1 output high voltage (port 0 in external bus mode) i oh = 800 m a, i oh = 300 m a i oh = 80 m a 2.4 0.75v cc 0.9v cc v v v i il logical 0 input current, ports 1, 2, 3 7 v in = 0.45v 50 m a i tl logical 1-to-0 transition current, ports 1, 2, 3 7 see note 4 650 m a i li input leakage current, port 0 v in = v il or v ih + 10 m a i cc power supply current (does not include ai cc ): 7 active mode @ 16mhz 5 idle mode @ 16mhz power down mode see note 6 11.5 1.3 3 25 5 50 ma ma m a r rst internal reset pull-down resistor 50 300 k w c io pin capacitance (i/o pins only) 10 pf notes: 1. typical ratings are not guaranteed. the values listed are at room temperature, 5v. 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus oper ations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v cc specification when the address bits are stabilizing. 4. pins of ports 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition current r eaches its maximum value when v in is approximately 2v. 5. i cc max at other frequencies is given by: active mode; i cc max = 1.43 freq + 1.90: idle mode; i cc max = 0.14 freq +2.31, where freq is the external oscillator frequency in mhz. i cc max is given in ma. see figure 12. 6. see figures 13 through 16 for i cc test conditions. 7. these values apply only to t amb = 0 c to +70 c. for t amb = 40 c to +85 c. see table on previous page.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 17 ac electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 10% (87c550), v cc = 5v 20% (80/83c550), v ss = 0v 1, 2 16mhz clock variable clock symbol figure parameter min max min max unit 1/t clcl 5 oscillator frequency: speed versions s8xc550 exx 3.5 16 mhz t lhll 5 ale pulse width 85 2t clcl 40 ns t avll 5 address valid to ale low 7 t clcl 55 ns t llax 5 address hold after ale low 27 t clcl 35 ns t lliv 5 ale low to valid instruction in 150 4t clcl 100 ns t llpl 5 ale low to psen low 22 t clcl 40 ns t plph 5 psen pulse width 142 3t clcl 45 ns t pliv 5 psen low to valid instruction in 82 3t clcl 105 ns t pxix 5 input instruction hold after psen 0 0 ns t pxiz 5 input instruction float after psen 37 t clcl 25 ns t aviv 5 address to valid instruction in 207 5t clcl 105 ns t plaz 5 psen low to address float 10 10 ns data memory t rlrh 6, 7 rd pulse width 275 6t clcl 100 ns t wlwh 6, 7 wr pulse width 275 6t clcl 100 ns t rldv 6, 7 rd low to valid data in 212 5t clcl 165 ns t rhdx 6, 7 data hold after rd 0 0 ns t rhdz 6, 7 data float after rd 55 2t clcl 70 ns t lldv 6, 7 ale low to valid data in 350 8t clcl 150 ns t avdv 6, 7 address to valid data in 397 9t clcl 165 ns t llwl 6, 7 ale low to rd or wr low 137 247 3t clcl 50 3t clcl +50 ns t avwl 6, 7 address valid to wr low or rd low 120 4t clcl 130 ns t qvwx 6, 7 data valid to wr transition 12 t clcl 50 ns t whqx 6, 7 data hold after wr 12 t clcl 50 ns t rlaz 6, 7 rd low to address float 0 0 ns t whlh 6, 7 rd or wr high to ale high 22 102 t clcl 40 t clcl +40 ns external clock t chcx 9 high time 20 20 ns t clcx 9 low time 20 20 ns t clch 9 rise time 20 20 ns t chcl 9 fall time 20 20 ns shift register t xlxl 8 serial port clock cycle time 750 12t clcl ns t qvxh 8 output data setup to clock rising edge 492 10t clcl 133 ns t xhqx 8 output data hold after clock rising edge 8 2t clcl 117 ns t xhdx 8 input data hold after clock rising edge 0 0 ns t xhdv 8 clock rising edge to input data valid 492 10t clcl 133 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100pf, load capacitance for all other outputs = 80pf.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 18 explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t pxiz ale psen port 0 port 2 a0a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t lhll t plph t lliv t plaz t llpl t aviv su00006 t pliv figure 5. external program memory read cycle ale psen port 0 port 2 rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t lldv t llwl t rlrh t llax t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv su00025 figure 6. external data memory read cycle
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 19 t llax ale psen port 0 port 2 wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx su00069 figure 7. external data memory write cycle 012345678 instruction ale clock output data write to sbuf input data clear ri valid valid valid valid valid valid valid valid set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv su00027 123 0 4567 figure 8. shift register mode timing v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 9. external clock drive
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 20 v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00717 figure 10. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00011 figure 11. float waveform 30 25 20 15 10 5 4mhz 8mhz 12mhz 16mhz freq at xtal1 max active mode typ active mode max idle mode typ idle mode i cc ma su00201 figure 12. i cc vs. freq (commercial temp. range) valid only within frequency specifications of the device under test
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 21 v cc p0 ea rst xtal1 xtal2 v ss v cc v cc v cc i cc (nc) clock signal p1 su00202 figure 13. i cc test condition, active mode all other pins are disconnected v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal p1 su00203 figure 14. i cc test condition, idle mode all other pins are disconnected v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 15. clock signal waveform for i cc tests in active and idle modes t clch = t chcl = 5ns v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) p1 su00204 figure 16. i cc test condition, power down mode all other pins are disconnected. v cc = 2v to 5.5v.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 22 eprom characteristics the 87c550 is programmed by using a modified quick-pulse programming ? algorithm. it differs from older methods in the value used for v pp (programming supply voltage) and in the width and number of the ale/prog pulses. the 87c550 contains two signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as an s87c550 manufactured by philips. table 4 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. the circuit configuration and waveforms for quick-pulse programming are shown in figures 17 and 18. figure 19 shows the circuit configuration for normal program memory verification. quick-pulse programming the setup for microcontroller quick-pulse programming is shown in figure 17. note that the 87c550 is running with a 4 to 6mhz oscillator. the reason the oscillator needs to be running is that the device is executing internal address and program data transfers. the address of the eprom location to be programmed is applied to ports 2 and 3, as shown in figure 17. the code byte to be programmed into that location is applied to port 0. rst, psen and pins of ports 1 and 2 specified in table 4 are held at the `program code data' levels indicated in table 4. the ale/prog is pulsed low 25 times as shown in figure 18. to program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1fh, using the `pgm encryption table' levels. do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. to program the security bits, repeat the 25 pulse programming sequence using the `pgm security bit' levels. after one security bit is programmed, further programming of the code memory and encryption table is disabled. however, the other security bit can still be programmed. note that the ea /v pp pin must not be allowed to go above the maximum specified v pp level for any amount of time. even a narrow glitch above that voltage can cause permanent damage to the device. the v pp source should be well regulated and free of glitches and overshoot. program verification if security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. the address of the program memory locations to be read is applied to ports 2 and 3 as shown in figure 19. the other pins are held at the `verify code data' levels indicated in table 4. the contents of the address location will be emitted on port 0. external pull-ups are required on port 0 for this operation. if the encryption table has been programmed, the data presented at port 0 will be the exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verification data. the encryption table itself cannot be read out. reading the signature bytes the signature bytes are read by the same procedure as a normal verification of locations 030h and 031h, except that p1.0 and p1.1 need to be pulled to a logic low. the values are: (030h) = 15h indicates manufactured by philips (031h) = 96h indicates s87c550 program/verify algorithms any algorithm in agreement with the conditions listed in table 4, and which satisfies the timing specifications, is suitable. table 4. eprom programming modes mode rst psen ale/prog ea /v pp p2.7 p2.6 p1.1 p1.0 read signature 1 0 1 1 0 0 0 0 program code data 1 0 0* v pp 1 0 1 1 verify code data 1 0 1 1 0 0 1 1 pgm encryption table 1 0 0* v pp 1 0 1 0 pgm security bit 1 1 0 0* v pp 1 1 1 1 pgm security bit 2 1 0 0* v pp 1 1 0 0 notes: 1. '0' = valid low for that pin, '1' = valid high for that pin. 2. v pp = 12.75v 0.25v. 3. v cc = 5v 10% during programming and verification. * ale/prog receives 25 programming pulses while v pp is held at 12.75v. each programming pulse is low for 100 m s ( 10 m s) and high for a minimum of 10 m s. ? trademark phrase of intel corporation.
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 23 a0a7 1 1 1 46mhz +5v pgm data +12.75v 25 100 m s pulses to ground 0 1 0 a8a11 p3 rst p1.0 p1.1 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.4 87c550 av cc av ss su00205 figure 17. programming configuration ale/prog: ale/prog: 1 0 1 0 25 pulses 100 m s+ 10 10 m s min su00018 figure 18. prog waveform a0a7 1 1 1 46mhz +5v pgm data 1 1 0 0 enable 0 a8a11 p3 rst p1.0 p1.1 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.4 87c550 av cc av ss su00206 figure 19. program verification
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 24 eprom programming and verification characteristics t amb = 21 c to +27 c, v cc = 5v 10%, v ss = 0v (see figure 20) symbol parameter min max unit v pp programming supply voltage 12.5 13.0 v i pp programming supply current 50 ma 1/t clcl oscillator frequency 4 6 mhz t avgl address setup to prog low 48t clcl t ghax address hold after prog 48t clcl t dvgl data setup to prog low 48t clcl t ghdx data hold after prog 48t clcl t ehsh p2.7 (enable ) high to v pp 48t clcl t shgl v pp setup to prog low 10 m s t ghsl v pp hold after prog 10 m s t glgh prog width 90 110 m s t avqv address to data valid 48t clcl t elqz enable low to data valid 48t clcl t ehqz data float after enable 0 48t clcl t ghgl prog high to prog low 10 m s programming * verification * address address data in data out logic 1 logic 1 logic 0 t avqv t ehqz t elqv t ehsh t shgl t ghsl t glgh t ghgl t avgl t ghax t dvgl t ghdx p3.0p3.7 p2.0p2.4 port 0 ale/prog ea /v pp p2.7 enable su00207 note: * for programming verification, see figure 17. for verification conditions, see figure 19. figure 20. eprom programming and verification
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 25 dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 26 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 27 notes
philips semiconductors product specification 80c550/83c550/87c550 80c51 8-bit microcontroller family 4k/128 otp/rom/romless, 8 channel 8 bit a/d, watchdog timer 1998 may 01 28 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 05-98 document order number: 9397 750 03853
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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